Field of the Invention
The present invention relates to a method for fabricating a high coupling ratio flash memory with a very narrow tunnel layer.
Memory technology has progressed considerably in recent years. High speed erasing is a popular method for improving the performance of a memory. Flash memories have a very high speed erasing feature in either an overall region or a local region thereof, therefore they are very popular in the computer field. For example, they are used to replace the read-only memories (ROMs) to store the firmware such as the BIOS (basic input output system), thus allowing the user to upgrade his/her BIOS by rewriting the flash memory, without the need of using another new memory. The flash memory has two layers of gates where an outer layer is a control gate and an inner layer is a float layer. The read/write manner of this flash memory is effected by means of electrons transferred between the float gate and source/drain gate. There is resulted in a coupling ratio which is defined as a ratio of an induced voltage on the float gate to the incident voltage applied on the flash memory. It is known that the higher the coupling ratio, the higher the efficiency of the flash memory. Conventionally, the coupling ratio is increased by increasing the areas of the opposite surfaces of the control gate and the float gate. However, for the high density requirement, the size of the memory chip is desired to be minimized, thus it is not easy to simultaneously minimize the size of the chip and still retain the coupling ratio in a high value.
It is known that NEC (an electrical company in Japan) has developed a new flash memory which has high density and high coupling ratio feature. The flash memory developed by NEC is made by a 0.4-micrometer procedure and is powered by a 3-volt voltage. This kind of flash memory defines a very small area of tunnel region (i.e., a thicker gate oxidizing layer relative to the channel region) between the float gate and the source/drain for decreasing the parasitic capacitance between the float gate and the substrate, thereby increasing the coupling ratio of the flash memory. The procedure for making the flash memory is described below by taking a reference to FIGS. 2A to 2F. Firstly, form a channel region as shown in FIG. 2A, where a local field oxidation procedure is performed on a P-type substrate to form a field oxide region FOX on the substrate, and overlapped layers of a gate oxide layer GOX, a first polysilicon layer 60, an oxidation layer OX, and a silicon nitride 50 formed on another portion of the substrate with a distance to the field oxide region FOX, thus defining a channel region under the gate oxide layer GOX. Secondly, perform an N.sup.+ source/drain ions implanting step to form N.sup.+ source/drain regions 5 in the substrate substantially around two sides under of the polysilicon 60; form two side walls of silicon nitride 51 respectively attached to two vertical sides of the polysilicon layer 60 via a silicon nitride deposition/reverse etching step; form thick oxide layers OX above the two N.sup.+ source/drain regions 5. Thirdly, remove the silicon nitride layer 50, the side walls of silicon nitride 51, and grow a very thin silicon oxynitride tunnel 70 (about 75 .ANG.) on an end portion of the N.sup.+ source/drain regions 5, and deposit a second polysilicon layer 80 on the overall surface. Fourthly, remove portions of the polysilicon layer 80 and leave two side walls of a second polysilicon layer 81 attached to two vertical oxide walls OX which are attached to two vertical sides of the first polysilicon layer 60. Fifthly, remove the oxide layer OX on the top surface of the first polysilicon layer 60 and deposit a third polysilicon layer 82 on the overall surface, so that the third polysilicon layer 82 can integrate with the first polysilicon layer 60 and the second polysilicon layer 81 and forms a float gate P1 as shown in FIGS. 2E and 2F. Sixthly, deposit a dielectric layer ONO on the top surface of the float gate P1 and deposit a fourth polysilicon layer P2 which functions as a control gate P2 thus forming a flash memory.
The flash memory as formed above, utilizes the side wall of the silicon nitride 51 to automatically align to the end portion of the N.sup.+ source/drain region 5, thus forming a very narrow tunnel region 70. Since a relatively thick gate oxide layer GOX isolates the float gate P1 from the substrate, a parasitic capacitance between the float gate P1 and the substrate is decreased considerably, therefore, the coupling rate is increased correspondingly. The two side walls of a second polysilicon layer 81 cause the recently formed float gate P1 and the control gate P2 to have an increased relative surface, thus increasing the coupling ratio.
However, the conventional flash memory suffers two drawbacks for establishing the high coupling ratio. Firstly, the conventional flash memory utilizes too many steps in forming different polysilicon layers thus resulting in the procedure to be very complicated and increasing cost. Secondly, since there are altogether four layers of polysilicon layers formed, the step height during the manufacture of the flash memory is correspondingly increased, which is not good for the flat requirement of semiconductor manufacture,